The present invention relates to semiconductor devices, and more specifically, to three-dimensional (3D) transistor devices.
Recent semiconductor fabrication methods have been developed to replace all or a portion of pure silicon (Si) fins with silicon germanium (SiGe) material, especially in p-type finFET devices. SiGe material reduces the threshold voltage (Vt) of a p-type semiconductor device, thereby increasing the drive current that flows through the channel. Further, SiGe material provides higher carrier mobility than fins consisting of only Si. Accordingly, SiGe fins typically have improved hole mobility performance compared to Si fins. The benefits of SiGe material described above have led to design trends that form fins with embedded SiGe (eSiGe) source/drain regions.
Referring to FIGS. 1-2, a conventional method of forming a finFET device 100 including eSiGe source/drain regions is illustrated. Conventional methods typically utilize only a single spacer layer followed by a directional etch to expose the underlying Si source/drain regions 102 of the fin while forming a single pair of spacers 104 on opposing sidewalls of the gate structure 106 (see FIG. 1). The exposed Si source/drain regions 102 are utilized as seed regions capable of epitaxially growing a semiconductor material therefrom.
Conventional eSiGe source/drain regions 108 typically include an epitaxially grown SiGe buffer layer 110 interposed between the original Si source/drain regions 102 and a subsequently grown highly-doped main SiGe layer 112 as further shown in FIG. 2. When performing a thermal anneal process to activate dopants of the main SiGe layer 112, for example, the buffer layer 110 serves to inhibit dopants of the highly-doped main SiGe layer 112 from diffusing into the fin channel region to prevent source/drain-channel shorting.
However, due to the natural asymmetrical directional growth of SiGe from Si, the SiGe buffer layer 110 is formed having an asymmetrical shape as further illustrated in FIG. 2. For example, the side portions 114a of the SiGe buffer layer 110 (i.e., grown from the Si sidewalls of the fin 102) are thinner than the base portions 114b (i.e., grown on the lower portion of Si source/drain regions of the fin 102). This asymmetrical shape (i.e., thickness delta) causes a non-uniform extension junction profile from the top of the fin channel to the bottom of the fin channel which can potentially affect the overall performance of the finFET device. For instance, the side portions 114a of the buffer layer 110 have a first total height (H1) while the highly-doped main SiGe layer 112 has a second total height (H2) that is less than H1. Consequently, a non-uniform eSiGe junction is formed, particularly at the corner region 116 of the buffer layer 110.